Power Aware & High Speed Booth Multiplier based on Adiabatic Logic

Multiplier is one of the major arithmetic operations carried out in DSP applications. This paper presents a modified Booth multiplier based on adiabatic logic. It is composed of Booth encoder, multiplier containing partial product generators and 1-bit (half and full) adders and final adder. Booth multiplication allows for smaller, faster multiplication circuits through encoding the signed numbers to 2’s complement. All circuits are realized with DTGAL (Dual Transmission Gate Adiabatic Logic) circuits using 0.25 μm technology. The power of proposed adiabatic Booth multiplier is compared with its corresponding CMOS implementation. It is observed from the device level simulation using TANNER EDA that the power consumption of the proposed multiplier has been reduced by 90% conventional CMOS multiplier.